It has been noted this framework doesn't work well under load, resulting in CRC mismatches & random RX timeouts etc. Discussion can be found here. I have observed the same behaviour. This example ...
#define PIN_STEP_0 GPIO_NUM_15 //STEP cancela #define PIN_DIR_0 GPIO_NUM_14 //DIR cancela #define PIN_STEP_1 GPIO_NUM_12 //STEP porta 1 #define PIN_DIR_1 GPIO_NUM_13 //DIR porta 1 #define PIN_SLEEP ...
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